 |
|
|
|
Conference Highlights
In-Stat forums are a rare combination of breaking news, insightful analysis, and non-stop networking. MPF Fall draws the audience you want to reach most—the industry’s best.
Hear the first public disclosures of new microprocessors, DSPs, and related embedded technologies, presented by their chief architects.
Includes a full-day seminar on Monday (Oct. 9) on one of today’s hottest topics led by a Microprocessor Report award-winning analyst.
Leading organizations to present on PC processors, server processors, low-power embedded processors, consumer embedded, imaging DSPs, and on the challenges of advanced semiconductor design.
For more information:
Elaine Potter
1.480.483.4441
epotter@reedbusiness.com |
|
|
| 8:35am |
Keynote: Energy Efficient Performance: The Next Frontier
Dr. Dileep Bhandarkar, Architect-at-Large, Digital Enterprise Group, Intel |
| 9:20am |
Session One: New Server Architecture
Many of today's tough design challenges and rewards converge on processors for servers. Their workloads can take advantage of high frequency operation, multiprocessing, and multithreading. The attainment of very high frequency is far from trivial. Moore's Law can be invoked to support multicore configurations and sophisticated cache hierarchies but power consumption and high temperature limitations make designs more complex than ever before. The server session will feature presentations from AMD, Fujitsu, IBM, and Sun. The four presentations will underscore different types of designs employing high frequency operation, multiple cores, and multiple threads with power management and performance tuning to take best advantage of system memory hierarchy. |
|
Fujitsu SPARC64 VI: A State of the Art Dual-Core Processor
presented by Aiichiro Inoue, Chief Scientist, Server Systems Group, Fujitsu Limited
Power6: IBM’s Next Generation Microprocessor
presented by Dr. Brad McCredie, IBM Fellow, POWER6 Chief Engineer, IBM
Niagara2 - A Highly-Threaded Server-on-a-Chip
presented by Robert Golla, Principal Architect, Sun Microsystems
Core Optimizations for System-Level Performance
presented by Ben Sander, Principal Member of Technical Staff, AMD |
| 12:45pm |
Keynote: Performance, Power and Function - Optimizing chip design for the new Generation
Ted Vucurevich, CTO, Cadence Design Systems |
| 1:30pm |
Session Two: Processor Cores
MPF Fall 2006’s core session exemplifies the trends in processor designs for embedded applications. Introductions of complete DSP subsystem platforms, high-performance low power DSP execution via clustered engines, and advances in performance and low power processors implemented in FPGAs will be presented by CEVA, ITRI, and Xilinx. |
|
RISC-free Voice over IP System Architecture
presented by Yair Siegel, Senior Applications Engineer and co-authored by Konstantin Merkher,VoIP Applications Manager, Ceva, Inc.
PAC Digital Signal Processor
presented by Dr. David Chih-Wei Chang, Deputy General Director, SoC Technology Center, Industrial Technology Research Institute
A High-Performance FPGA-Based System Architecture
presented by Ralph Wittig, Director, Embedded Processing Division, Xilinx, Inc.
|
| 3:25pm |
Session Three: Multicores for Embedded Applications/Part One
It seems that just a few years ago, multiple-core processors made a brief appearance only to quickly fade into the background. Their design configuration was powerful, but at the time few OEMs were worried about power consumption or cost of custom SoC implementations in sub-90nm semiconductor processes. Multiple-core embedded processors are back offering a less expensive configurable programmable alternative to custom SoCs. Multiple-core engines can take on workloads such as general purpose multithreading, DSP for infrastructure applications, security, and networking. MPF Fall’s two sessions on multiple cores for embedded applications include presentations from Ambric, ARC International, Boston Circuits, Cavium, Emulex, Eutecus, Optosecurity, and Renesas. |
|
A Power-Efficient TeraOPS IC Employs Massively-Parallel Architecture
presented by Mike Butts, Ambric Fellow and IC Architect, Ambric, Inc.
Efficient Multi-Processing for Media Applications
presented by Nigel Topham, Chief Architect, ARC International
The Multi-Core Architecture of the gCORE16
presented by Hiro Kataoka, President and CEO, Boston Circuits, Inc.
A Multi-Cell Massively Parallel Sensor-Processor Architecture
presented by Dr. Akos Zarandy, Chairman, V. P. of Technology and Co-CTO of Eutecus, Inc. |
|
|
|
|
|
|
