I/O, I/O, Changing the Status Quo: Chip-to-Chip Interconnects
Non-proprietary I/O is seeing an increasing presence within the central processing, printed circuit board, and IP communities. HyperTransport, PCI Express, and RapidIO benefit from the strength of central special interest groups (SIG). The SIG becomes the central point of aggregation for improving I/O standards. HyperTransport 3.0 increased frequency from 1.4GHz per trace line to 2.6GHz per line. PCI Express, the standard which currently has a 2.0 revision before its membership, increases the effective frequency from 2.5GHz to 5GHz. Serial RapidIO also has a 2.0 revision before its members that increases frequency from 3.125Gbaud to 6.25Gbaud. The increased bandwidths serve to make the I/O more functional, but the non-proprietary I/O is stretching out to new usages. In PCI Express 2.0, the PCI-SIG is developing standards for cabling as well as defining single-root virtualization I/O. With HyperTransport 3.0, methods for power consumption as well as for cabling are introduced. The RapidIO Trade Association, for Serial RapidIO 2.0, helped to define a new Management and Flow Control mechanism that can process payloads of as many as 64KB from 64,000 different senders. This In-Stat report examines what the implications of changes in the I/O means on a device level. For example, the I/O requirements are different for portable devices than for personal computers. The usages of HyperTransport, PCI Express, and RapidIO are forecast for devices from 2004-2010.
