Microprocessor Forum
Wednesday October 15th

Conference

Keynote:
The History and Future of Computer Instruction Set Architectures
Fred Weber, CTO & Vice President, Computation Products Group, Advanced Micro Devices

Session 3:
High-performance Processors
Markus Levy, Senior Analyst, In-Stat/MDR

High Performance Processor for Deeply Embedded Applications
John Rayfield, VP of US Marketing, ARM

Practical Benefits of Multi-Threaded RISC/DSP Processing
David W. Knox, Vice-President, Software, Imagination Technologies

MIPS Technologies New MIPS32, 24K Family of 32-bit Cores Offers the Fastest, Synthesizable, Licensable Processor Intellectual Property
Kevin D. Kissell, Architect, MIPS Technologies

New 32-bit Family from MIPS Technologies Offers the Fastest Synthesizable Licensable Processor Core
Larry Hudepohl, Engineering Director, MIPS Technologies

Session 4:
Low-Power Processors
Max Baron, Principal Analyst, In-Stat/MDR

ARC Unveils Next-Generation ARCtangent A600 Processor
Dr. Nigel Topham, Chief Architect, ARC International

Mobile Applications Processor with Enhanced Security
Simon Segars, Vice President, Engineering, ARM

SH-X: 4500MIPS/W 2-Way Superscalar CPU Core and its SoC Products
Shinichi Yoshioka, SH-X Project Manager, SoC Division, Renesas Technology Corp.

Next-Generation Processor Architecture for Innovative Convergence Platforms
John Vaglica, Manager, Advanced SoC Architecture Team, Motorola, Inc.

Special Presentation - "TRIPS: Extending the Range of Programmable Processors
Stephen W. Keckler, Assistant Professor, The University of Texas at Austin

Panel:
"The End of Conventional Architectures"
moderated by Peter N. Glaskowsky, Principal Analyst, In-Stat/MDR

MORE >