Microprocessors for Professionals - Webinar

Microprocessors for Professionals is an exciting new Web-based seminar for marketing managers, public relations specialists, financial analysts, venture capitalists, executives, attorneys, journalists, and others who need a plain-talk crash course on microprocessor technology.

It starts with the basics and covers such topics as microprocessor architectures, pipelining, superscalar execution, branch prediction, caches, semiconductor manufacturing, performance factors, the microprocessor's role in system-level designs, and how the evolution of technology is creating new business models.

A deeper knowledge of microprocessors is vital for anyone who needs to evaluate technology, perform competitive analysis, communicate with clients, and understand the latest developments. Microprocessors for Professionals definitely isn't for dummies. It's for intelligent professionals who need a thorough grasp of microprocessors to excel in their careers

Microprocessors for Professionals - Webinar Outline
Chapter 1: Microprocessors 101
  • Introduction
    • Seminar leader bio
    • Table of contents
    • What is a microprocessor?
    • Basic system architecture
    • Microprocessor history and progress
    • Mr. Microprocessor's neighborhood
    • Some more basic terminology
    • Transistors: the foundation
    • Resolving technobabble confusion
    • Gate-level logic
  • The Microprocessor's Universe
    • One step from entropy: yin and yang
    • Binary basics
    • The role of a microprocessor
    • The role of software
    • How instructions are born
    • Programming languages and compilers
    • Program instructions vs. program data
    • Assembly language
    • Conditional branches
    • Instructions ride to work on the bus
    • Instruction fetching
  • Chapter 1 Quiz (six questions and answers)
Chapter 2: Life Cycle of an Instruction
  • Instruction Flow
    • Instruction fetching
    • I-fetch illustration
    • Instruction decoding
    • Opcodes and instruction formats
    • Understanding registers
    • Using registers
    • Register address vs. register value
    • Example of registers in action
    • Anatomy of a register
    • Register widths and capacities
    • Integer and floating-point data types
    • Understanding endianness
    • Big endian vs. little endian
    • An actual instruction format
  • Instruction Execution
    • Function units and their role in execution
    • Writeback
    • Writeback example
    • Instruction-flow summary
  • Chapter 2 Quiz (six questions and answers)
Chapter 3: CPU Architecture
  • Introduction to CPU Architecture
    • Sorting out the technobabble
    • Example terminology and analogy
    • Architectural standards and examples
    • The "widths" of architectures
    • What does "32-bit processor" mean?
    • CPU incompatibility explained
    • The reasons for different architectures
  • CISC Architectures
    • The reasons for CISC
    • Direct-memory instructions
  • RISC Architectures
    • The reasons for RISC
  • RISC vs. CISC Analysis
    • RISC vs. CISC: code density
    • RISC vs. CISC instruction decoding
    • RISC vs. CISC register files
    • RISC vs. CISC load/store instructions
    • RISC vs. CISC complexity
  • VLIW Architectures
    • VLIW instructions
    • VLIW NOPs
    • VLIW processors
    • Transmeta's x86 VLIW
    • Transmeta code morphing
    • Transmeta tradeoffs
  • EPIC Architectures
    • EPIC instruction format
    • The reasons for EPIC
  • Architecture Summary
    • Future architectures
  • Chapter 3 Quiz (five questions and answers)
Chapter 4: CPU Microarchitecture
  • Introduction to CPU Microarchitecture
    • Technobabble review
    • The role of microarchitecture
    • Understanding clock speed
    • Microarchitectural differences
    • Microarchitecture vs. architecture
  • The Slow-Memory Challenge
    • Slow memory analogy
    • DRAM bandwidth
    • CPU front-side buses
    • Bus architectures
    • Harvard vs. von Neumann architectures
    • Serial vs. parallel buses
    • Types of buses in PCs
    • The bus speedometer
    • Wide vs. narrow buses
    • Fast vs. slow buses
    • Understanding bus clocking
    • Calculating bus bandwidth
    • Boosting bus speeds
    • Bus signaling
    • Double-clocked buses
    • Quadruple-clocked buses
    • Bus bandwidth trends
    • The latency problem
    • Understanding caches
    • Instruction and data caches
    • I-fetch and d-fetch
    • How caches work
    • Locality of reference
    • Cache snooping
    • Multilevel caches
    • Cache summary
  • Memory Addressing
    • Memory addressing example
    • PC memory architecture
    • CPUs with integrated memory control
  • Chapter 4 Quiz (five questions and answers)
Chapter 5: Instruction Pipelining
  • Introduction to Instruction Pipelining
    • Pipeline analogy: factory assembly line
    • Instruction-flow review
    • Pipeline theory
    • Single-cycle execution
    • Pipelining: example animation
    • Pipeline depths
    • Pipeline tradeoffs
  • Branch Prediction
    • Understanding branch prediction
    • Dynamic branch prediction
    • Static branch prediction
    • Speculative execution
    • Speculation example
  • The Myth of Multitasking
    • Multitasking by context switching
    • Context-switching: example animation
    • Context-switching penalties
    • Simultaneous multithreading
    • Simultaneous multithreading: example animation
    • Multiple register files
  • Superscalar Pipelining
    • Reasons for superscalar pipelining
    • Two-way superscalar
    • Superscalar problems
    • Resource and data dependencies
  • Out-of-Order Execution
    • Reasons for rearranging instructions
    • Out-of-order execution example
    • Tradeoffs
  • VLIW and EPIC Alternatives
    • VLIW review
    • VLIW instruction scheduling
    • Problems with VLIW
    • EPIC innovations
  • How to Read a Block Diagram
    • Understanding block diagrams
    • Block diagram examples
    • Die photos and floorplans
  • Chapter 5 Quiz (six questions and answers)
Chapter 6: Semiconductor Manufacturing
(This chapter was contributed by consultant Jim Turley)
  • Introduction to Semiconductor Manufacturing
    • Basic technology and terminology
    • Making silicon wafers
    • Why size matters
    • Meet the fab
    • Inside a clean room
    • Lithography: photography writ small
    • How steppers work
    • Bonding pads
    • Packaging the chip
    • Transistor factoids
    • Process geometry
    • Anatomy of a transistor
    • Process shrinks
  • Semiconductor Economics 101
    • Revenue and unit-sales breakdowns
    • Staggering capital costs
    • Incremental manufacturing costs
    • Advantages of larger wafers
    • Gross die per wafer
    • Wafer defects and chip yields
    • Analyzing the cost of a chip
  • More About Process Geometry
    • Process shrinks vs. design shrinks
    • Pad-limited chips
    • Product-line sleight of hand
  • Vocabulary review
  • Chapter 6 Quiz (six questions and answers)
Chapter 7: Microprocessor Trends
  • Technology Drives Business
    • Evolving business models
    • Traditional, fabless, and IP models
    • Traditional semiconductor companies
    • The traditional food chain
    • Fabless semiconductor companies
    • The fabless food chain
    • IP companies and core licensing
    • The core-IP food chain
  • Microprocessor Cores
    • Core integration and SoCs
    • Hard cores vs. soft cores
    • Is it hardware or software?
    • Trend: CPUs get softer
  • Customizable CPU Cores
    • Configurable vs. extendable
    • Feedback-driven design flow
    • Customizable CPU vendors
    • Graphical design tools
    • Anybody can design a chip!
    • Benchmark benefits of customizable CPUs
    • The future of soft microprocessors
  • Overall Future Trends
    • Understanding Moore's law
    • Distorting Moore's law
    • The truth about Moore's law
    • Moore's law vs. reality
    • Trend: miniaturization
    • Trend: higher integration
    • Trend: pervasive computing
    • Trend: tighter security
    • What's next?
  • Chapter 7 Quiz (five questions and answers)

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