Much of what drives today’s electronics industry revolves around consumer video. From the technologies and infrastructure required to deliver video, to the client devices that offer high definition quality and mobility to users at home and on the go, companies of all types are spending vast quantities of money to appease today’s video hungry consumer.

Microprocessor Forum’s Expo and Demo Showcase 2007 will be host to some of today’s most spectacular technology demonstrations and to hundreds of consumers of those technologies.

This year’s Expo and Demo Showcase will feature the following exciting demonstrations: Full List of exhibitors >

Intel’s 80-core Teraflops Research Processor represents an important milestone towards enabling future processors with 10s to 100s of cores for PCs and Servers. It is first programmable chip to deliver more than one trillion floating point operations per second (1 Teraflops) of performance -- while consuming very little power. This prototype focuses on exploring scalable, energy–efficient designs for future multi–core chips as well as core–to–core interconnect and clocking. The 65nm 100M transistor die achieves 1.01 TFlops of peak performance at 0.95V, while dissipating 62W.
 
Atmel will demonstrate the Development Board for a new product family that combines the benefits of a ready-to-use microcontroller with the application-orientation of an ASIC. The highly integrated System-on-Chip reduces development time, cost and risk for new applications, and provides a low-cost replacement for existing applications built around a microcontroller standard product and an FPGA.
 
Calypto will be demonstrating its recently announced PowerProTM CG product which reduces power in RTL designs by up to 60% and its SLEC™ verification products which find bugs that others tools miss.

PowerPro CG is and automated power optimization solution that has reduced power with little or no impact on timing or area. The PowerPro CG demonstration will include:

  • Viewing power saving results from various sequential power reductions across multiple designs
  • Interactively identifying and applying RTL power transformations and seeing the effects on timing, area and power
  • Show interoperability of PowerPro CG with RTL synthesis tools through common file formats

SLEC is a Sequential Logic Equivalence Checker that functionally verifies RTL designs without testbenches or assertions. This year the SLEC demonstration will show:

  • How to efficiently find and fix design bugs using the latest SLEC reporting features
  • A system-level methodology for RTL verification using expanded SLEC setup features
  • Comprehensive verification of sequential power optimizations with SLEC clock-gating capabilities
 
Codeplay will show Sieve-enabled Fractal and Image Generators on an Intel quad-core x86, on Cell and on a dual-core x86 with the Ageia PhysX card. For the gamers present, we'll show the latest version of Cell Factor running with the Ageia PhysX card - it's stunning and our compiler helped!
 
RAVEN generates random sequences of assembly code from a user created test template. The code sequences are used to functionally verify the design of a processor or DSP. RAVEN generated tests include the initial conditions, the assembly code, any intermediate data, and the final state of the machine.
 

Target’s Chess/Checkers tool-suite is used to design, optimize, program and verify application-optimized processor cores (ASIPs). VLIW, SIMD, and ultra-low power architectures are our specialty. Typical application domains include:

  • Video/audio/media processing (e.g. decode/encode, fidelity enhancement)
  • Mobile devices (e.g. hand-held media players)
  • Wireless communications (e.g. baseband processing)
  • Datacom/Telecom (e.g. packet processing)
  • Security (e.g. IPSec)
  • And many others

We will demonstrate the keystone of our tool-suite - our unique retargetable C compiler, which enables rapid application-focused processor architecture optimization as well as efficient algorithm mapping to the final architecture.
 

Demo highlights

  • OSTI business case: secure Linux® and open Windows CE® on single core platforms
  • OMTP security requirements with Trusted Execution
  • Secure dynamic update of Windows CE and Linux
  • PCI-PED ready solution for single core point of sales platform
  • Full SDK, including ECLIPSE plug-in
  • Support of low-end to high-end mobile platforms

Benefits for SoC vendors, OEM and operators:

  • Reduce BOM and cut validation costs
  • Secure critical functions, and build robust and reliable devices
  • Integrate market standards and isolate proprietary code from GPL license constraints
  • Cut certification costs (point-of-sales PCI PED, set-top-box...)
 
Simulation of heterogeneous multi-core embedded systems, executing on a standard PC. The simulation performance is fast enough to execute real-world software applications such as operating systems, video, and audio decoding algorithms at near real-time speed. Fast, accurate models for processor and bus families including ARM, PPC, MIPS, DSPs, AHB, AXI and PCI. Modeling of hardware features, such as cache coherency, pipelining, and branch prediction with cycle accuracy. Support for peripheral models written in C or SystemC, and co-simulation with logic and behavioral simulators. The resulting virtual platforms are invaluable for modeling architectural tradeoffs, verification, and concurrent development of software and hardware.