Redefining Performance Through System Balance presented by Chuck Moore, Senior Fellow, AMD At one time, our industry focused all its attention on the raw speed of the microprocessor core, but today’s picture is much different. In this talk, AMD Senior Fellow Chuck Moore will examine these important new aspects of processor chip design. In particular, he will discuss the role of power efficiency, on-chip system architecture, chip multiprocessing, throughput performance, modularity, and flexibility.

Session One
Advances in DSP Engines

Digital signal processing is the fastest evolving branch of computing with applications that have made their way into the home, office, and automobile, and the broad spectrum of portable wireless, audio, imaging, and video devices. The DSP products presented in this session exemplify the wide range of power-efficient architectures offered ranging from coprocessing accelerators built to enhance general-purpose engines, through DSP cores, and up to homogeneous and heterogeneous multicores.

Presentations

The Elemental Computing Architecture
presented by Paul Master, Director of Technology, Element CXI

Freescale's Developments on the newest Core Architecture from StarCore
presented by Zvika Rozenshein, Director, DSP Cores and Platforms, Freescale Semiconductor

Freescale's high performance DSP aims at next generation converged networks
presented by Odi Dahan, Chief Architect, DSP SoC Design, Freescale Semiconductor, Israel

F1: TI's Implementation of ARM Cortex-A8
presented by Ty Garibay, ARM Cores Program Manager, TI Wireless Terminal Business Unit, Texas Instruments.

Session Two
Next-Generation Licensable Processors & IP

Licensable processors and related IP cores are indispensable for designing the ASICs and SoCs in embedded systems. The growing demand for power-efficient processing is driving the evolution of licensable IP in exciting new directions. This session includes breakthrough presentations about the first commercially available clockless 32-bit processor core, the first licensable multithreaded processor core, a new low-power 32-bit embedded processor, a new IP platform for chip design, and a new low-power graphics coprocessor for portable consumer electronics.

Presentations

A New ARM Cortex Processor for Power-Efficient Embedded Systems
presented by Richard York, Product Manager, ARM

ARM996HS: The First Licensable, Clockless 32-Bit Processor Core
presented by Arjan Bink, Chief Design Engineer, Handshake Solutions

The ZEVIO Architecture for Consumer SoC Development
presented by Shinya Fujimoto, Principal Architect, LSI Logic

The MIPS32 34K Processor: Multithreading Optimizations in a Single-Issue Pipeline
presented by Darren Jones, Engineering Director, Microprocessor Development, MIPS Technologies, Inc.

Session Three
Technology for Power-Efficient Processing, Part 1

This mega-session is split over two forum days and provides the core presentations for our theme of power-efficient design. The session addresses a range of technology tools available to chip designers. The session’s seven presentations include a tool to estimate the energy and power requirements of a configurable and extendable IP core, design techniques that save power from some of the best in the industry, an example of power/performance considerations in floor-planning and pin locations on the ARM Cortex-A8, and benchmarking a final product against its competitors.

Presentations

Energy Estimator for Extensible Processor Platform
presented by Dr. Jagesh Sanghavi, Engineering Manager, Tensilica

Optimizing the power for multiple voltage domains
presented by Mark Hartman, Staff Applications Engineer, National Semiconductor

Day Two of the conference