IN0502448IN

Table of Contents

Introduction
Desktop Processors
- Best Desktop PC Processor of 2004
  - Close Race, but One Stands Above the Rest
  - Desktop Goes Dual Core in 2005
- IBM Takes the Lead
  - Performance Is Close to x86 Rivals
  - System Interface Sets Speed Record
- AMD vs. Intel in Dual-Core Duel
  - Sempron? What’s a Sempron?
  - Getting the Message Out
- Intel Launches Grantsdale Chipset
  - PCI Express Modifies the System Architecture
  - Migration to DDR2 and Enhanced RAID
  - Integrated Graphics Supporting DirectX 9.0
  - Audio and Wireless Features for the Home
  - Good Without the Hype
Mobile PC Processors
- Best Mobile PC Processor of 2004
  - More Exciting Mobile Processors to Come
- Intel Beats Intel for Mobile Crown
  - Last-Minute Controversy Is Par for the Course
- Intel’s PC Roadmap Sees Double
  - Hitting the Power Wall
  - Did AMD See “The Right-Hand Turn” Signal?
- How Is Intel Really Doing?
  - Intel Still on the Leading Edge of Technology
  - Intel Makes Some Visible Mistakes
  - What Does This Mean to the World’s Largest Chip Vendor?
  - The Future: What Should We Expect From Intel?
- AMD Revises ’05 Processor Roadmap
Server Processors
- Best Servers of 2004
  - And the Winner Is…
- ISSCC Promises Progress
  - Memory Density Rises, Power Plummets
  - Application-Specific Processors Flourish
- Apple Debuts 90nm G5 in Xserve
- Sun Rolls Forward With Rock
- Intel Addresses the 64-Bit Question
  - Itanium Roadmap Presages Xeon Conflict
  - A Bright Spot in Intel’s Future
  - AMD and Intel Harmonize on 64
  - Deciphering the Nomenclature
  - Comparing 64-Bit Instruction Sets
  - Faster Context Switching in x86-64
  - Deleted Instructions and Strange Differences
  - Register Files Are Fully Compatible
  - Memory Becomes Bigger and Flatter
  - 64-Bit Compatibility Good for Industry
  - Intel and AMD Manuals Sing Similar Tunes
- A Tale of Two Instructions
  - SAHF and LAHF: Never Say Die
  - Can’t We All Just Get Along?
- SPARC’s New Roadmap
  - Rock Gets a Push
  - If SPARC Fizzles
- Sun’s Niagara Pours on the Cores
- Gulliver vs. the Highly Threaded Lilliputians
- Double Your Opterons; Double Your Fun
  - Building the First Dual-Core AMD Processor
  - The Cores Get Enhancements As Well
  - Performance Scaling
  - AMD Still Has More Work to Do
  - The CMP Story Continues to Unfold
- SPARC Turns 90nm
  - Fujitsu Doubles Cores and Threads for APL
- Bringing Power to the People
  - Fifteen Companies Join IBM’s Bandwagon
  - The China Connection

List of Tables

Table 1.Top desktop processors for 2004.
Table 2. Summary of Intel chipsets.
Table 3. Latest generations of mobile processors available in 2004.
Table 4. Intel’s new 2H05–1H06 processor roadmap.
Table 5. Power consumption for different versions of the desktop Intel Pentium 4 processor.
Table 6. A new roadmap for Intel’s Itanium processor family.
Table 7. These are the ten “new” instructions in the 64-bit ISAs from AMD and Intel.
Table 8. Instructions listed in this table as “64-Bit Invalid” remain in the 32-bit x86 ISA but are no longer available to 64-bit programs.
Table 9. This is a summary of the similarities and differences between AMD’s AMD64 and Intel’s EM64T architectures.
Table 10. Key features of the present UltraSPARC processors and Niagara.
Table 11. A summary of UltraSPARC IV and IV+ features.

List of Figures

Figure 1. Die photo of Athlon 64 processor.
Figure 2. The 130nm PowerPC 970 used in Apple’s Power Mac G5.
Figure 3. AMD’s new processor roadmap introduces a plethora of new code names.
Figure 4. AMD’s former processor roadmap, from fall 2003.
Figure 5. The dual-core AMD processor will have two Opteron processor cores on one die.
Figure 6. This figure shows that the Opteron on-die memory controller was dual-processor capable all along.
Figure 7. Beon the lookout in 2H04 for AMD’s new processor brand—Sempron.
Figure 8. The AGP bus required arbitration between transmissions flowing in opposite directions between the graphics card and chipset.
Figure 9. Intel’s increased memory performance.
Figure 10. Picture of Dothan Pentium M core.
Figure 11. The Banias version of Intel’s Pentium M shows how much of the chip is devoted to cache memory.
Figure 12. Slide from Intel’s fall Analyst Meeting of November 20, 2003.
Figure 13. This graph shows the increase in standby current over the three most recent Pentium 4 processors.
Figure 14. Desktop and mobile PC forecast, with the adoption rate of PCI Express.
Figure 15. AMD processor roadmap as of November 24, 2004.
Figure 16. AMD processor roadmap as of July 2004.
Figure 17. AMD’s dual-core Opteron processor was sampled in 2004.
Figure 18. Die photo of the UltraSPARC IV+.
Figure 19. The Niagara processor has eight UltraSPARC II–like cores with a shared and banked L2 cache.
Figure 20. The Madison/9M version of the Itanium 2 is shown in the die photo.
Figure 21. With 1.72 billion transistors, the Montecito die has three times the number of transistors as the Madison/9M it will replace and is fabricated in Intel’s 90nm process.
Figure 22. This chart, adapted from the 64-bit programming manuals from AMD and Intel, shows that x86-64 processors have two new execution modes distinct from the existing 32-bit “legacy mode.”
Figure 23. The 64-bit ISAs from AMD and Intel both define the same register files, adding several new 64-bit registers and extending the 32-bit registers to 64 bits.
Figure 24. Sun Microsystems’s processor roadmap from early 2003.
Figure 25. Sun’s processor roadmap, from later in 2003.
Figure 26. Sun Microsystem’s new processor roadmap no longer includes Millennium and Gemini.
Figure 27. The basic block diagram of Sun’s Niagara processor.
Figure 28. The basic integer pipeline of the Niagara SPARC core has only a six-stage pipeline.
Figure 29. The core supports four threads and can treat each thread equally (round robin), but it will give a stalled thread priority when the thread is ready to resume.
Figure 30. AMD provided an update to its processor block diagram.
Figure 31. Die photo of the dual-core AMD Opteron processor.
Figure 32. The die photo of the UltraSPARC IV+.
Figure 33. This block diagram shows the numerous UltraSPARC IV+ core.
Figure 34. The L2 cache has greater flexibility and lower latency than the off-chip L2 in UltraSPARC IV.
Figure 35. The L3 cache interface for the US IV+ is based on the off-chip L2 cache of the US IV.
Figure 36. The system architecture of the UltraSPARC IV+.
Figure 37. Design reuse and layout mirroring sped the design process for SPARC64 VI.
Figure 38. A cut-away view of the transistor and interconnect structures of Fujitsu’s 90nm process.
Figure 39. The die layout of the 90nm SPARC 64 VI.
Figure 40. The Fujitsu SPARC processor roadmap from FPF04.